Bus Interconnection
A bus is a communication pathway connecting two or more devices, A key characteristic of a bus is that it is a shared transmission medium, Multiple devices connect to the bus, and a signal transmitted by any one device is available for reception by all other devices attached to the bus. If two devices transmit during the same time period, their signals will overlap and become garbled. Thus, only one device at a time can successfully transmit.
Typically, a bus consists of multiple communication pathways, or lines. Each line
is capable of transmitting signals representing binary 1 and binary 0. Over time, a sequence of binary digits can be transmitted across a single line. Taken together, several lines of a bus can be used to transmit binary digits simultaneously (in parallel).For example, an 8-bit unit of data can be transmitted over eight bus lines.
Computer systems contain a number of different buses that provide pathways
between components at various levels of the computer system hierarchy. A bus that
connects major computer components (processor, memory, I/O) is called a system
bus. The most common computer interconnection structures are based on the use of one or more system buses.
Bus Structure
A system bus consists, typically, of from about 50 to hundreds of separate lines. Each line
is assigned a particular meaning or function. Although there are many different bus designs, on any bus the lines can be classified into three functional groups (Figure 3.16):
Figure 3.16 Bus Interconnection Scheme
data, address, and control lines. In addition, there may be power distribution lines that
supply power to the attached modules.
The data lines provide a path for moving data between system modules. These lines, collectively, are called the data bus. The data bus may consist of from 32 to
hundreds of separate lines, the number of lines being referred to as the width of the
data bus. Because each line can carry only 1 bit at a time, the number of lines determines how many bits can be transferred at a time. The width of the data bus is a key factor in determining overall system performance. For example, if the data bus is 8 bits wide and each instruction is 16 bits long, then the processor must access the memory module twice during each instruction cycle.
The address lines are used to designate the source or destination of the data on the data bus. For example, if the processor wishes to read a word (8, 16, or 32 bits) of data from memory, it puts the address of the desired Word on the address lines. Clearly, the width of the address bus determines the maximum possible memory capacity of the system. Furthermore, the address lines are generally also used to address I/O pOrts. Typically, the higher-order bits are used to select a particular module on the bus. and the lower-order bits select a memory location or l/O port within the module. For example, on an 8-bit address bus, address O1IIILII and below might reference locations in a memory module (module 0) With L28 WOrdS ot memory, and address 10000000 and above refer to devices attached to an 1/O module (module 1).
The control lines are used to control the access to and the use of the data and address lines. Because the data and address lines are shared by all Components, there must be a means of controlling their use. Control singals transmit both command and timing information between syntax modules. Timing signals indicate the validity of data and address information. Command signals specify operations to be performed. Typical control lines include
• Memory write: Causes data on the bus to be written into the addressed location
• I/O read: Causes data from the addressed I/O port to be placed on the bus
• Transfer ACK: Indicates that data have been accepted from or placed on the bus
• Bus request: Indicates that a module needs to gain control of the bus
• Bus grant: Indicates that a requesting module has been granted control of the bus
Interrupt request: Indicates that an interrupt is pending
• Interrupt ACK: Acknowledges that the pending interrupt has been recognized
• Clock: Used to synchronize operations
• Reset: Initializes all modules
The operation of the bus is as follows. If one module wishes to send data to another, it must do two things: (1) Obtain the use of the bus, and (2) transfer data via the bus. If one module wishes to request data from another module, it must (1) obtain the use of the bus, and (2) transfer a request to the other module over the appropriate control and address lines. It must then wait for that second module to send the data. Physically, the system bus is actually a number of parallel electrical conductors. In the classic bus arrangement, these conductors are metal lines etched in a
Figure 2 Typical Physical Realization of a Bus Architecture
card or board (printed circuit board). The bus extends across all of the system components, each of which taps into some or all of the bus lines. The classic physical arrangement is depicted in Figure 2. In this example, the bus consists of two vertical columns of conductors. At regular intervals along the columns, there are attachment points in the form of slots that extend out horizontally to support a printed circuit board. Each of the major system components occupies one or more boards and plugs into the bus at these slots. The entire arrangement is housed in a chassis, This scheme can still be used for some of the buses associated with a computer system. However, modern systems tend to have all of the major components on the same board with more elements on the same chip as the processor. Thus, an on-chip bus may connect the processor and cache memory, whereas an on-board bus may connect the processor to main memory and other components.
This arrangement is most convenient. A small computer system may be acquired and then expanded later (more memory, more I/O) by adding more boards. If a component on a board fails, that board can easily be removed and replaced.
Multiple-Bus Hierarchies
If a great number of devices are connected to the bus, performance will suffer. There
are two main causes:
1. In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay. This delay determines the time it takes for devices to coordinate the use of the bus. When control of the bus passes from one device to another frequently, these propagation delays can
noticeably affect performance.
2. The bus may become a bottleneck as the aggregate data transfer demand approaches the capacity of the bus. This problem can be countered to some extent by increasing the data rate that the bus can carry and by using wider buses (e.g., inereasing the data bus from 32 to 64 bits). However, because the data rates generated by attached devices (e.g., graphics and video controllers,network interfaces) are growing rapidly, this is a race that a single bus is ultimately destined to lose.
Accordingly, most computer systems use multiple buses, generally laid out in a hierarchy. A typical traditional structure is shown in Figure 3a. There is a local bus
that connects the processor to a cache memory and that may support one or more local devices The cache memory controller connects the cache not only to this local bus, but to a system bus to which are attached all of the main memory modules. the use of a cache structure insulates the processor from a requirement to access main memory frequently. Hence, main memory can be
moved off of the local bus onto a system bus. In this way, I/O transfers to and from the main memory across the system bus do not interfere with the processor's activity. It is possible to connect I/O controllers directly onto the system bus. A more efficient solution is to make use of one or more expansion buses for this purpose. An expansion bus interface buffers data transfers between the system bus and the I/O
controllers on the expansion bus. This arrangement allows the system to support a
wide variety of I'O devices and at the same time insulate memory-to-processor traf-
fic from IO traffic.
Figure 3a shows some typical examples of I/O devices that might be attached to the expansion bus Network connections include local area networks(LANS) such as a 10-Mbps Ethernet and connections to wide area networks(WANS) such as a packet-switching network, SCSI (small computer system inter-
face) is itself a type of bus used to support local disk drives and other peripherals.
A serial port could be used to support a printer or scanner.This traditional bus architecture is reasonably efficient but begins to break
down as higher and higher performance is seen in the I/O devices. In response to
these growing demands, a common approach taken by industry is to build a high-speed bus that is closely integrated with the rest of the system, requiring only a bridge between the processor's bus and the high-speed bus. This arrangement is sometimes known as a mezzanine architecture.
Figure 3b shows a typical realization of this approach. Again, there is a local bus that connects the processor to a cache controller, which is in turn connected to a system
bus that supports main memory. The cache controller is integrated into a bridge, or
buffering device, that connects to the high-speed bus. This bus supports connections
to high-speed LANS such as Fast Ethernet at 100 Mbps, video and graphics workstation
controllers, as well as interface controllers to local peripheral buses, including SCSI and
Fire Wire. The latter is a high-speed bus arrangement specifically designed to support
high-capacity I/O devices Lower-speed devices are still supported off an expansion bus,
with an interface buffering traffic between the expansion bus and the high-speed bus.
The advantage of this arrangement is that the high-speed bus brings high-demand devices into closer integration with the processor and at the same time is independent of the processor. Thus, differences in processor and high-speed bus
Figure 3 Example Bus Configurations
speeds and signal line definitions are tolerated. Changes in processor architecture do not affect the high-speed bus, and vice versa.
Elements of Bus Design
Although a variety of different bus implementations exist, there are a few basic parameters or design elements that serve to classify and differentiate buses. Table 1
lists key elements.
Bus Types bus lines on be separated into two generic types: dedicated and Multiplexed. A dedicated bus line is permanently assigned either to one function or to a physical subset of computer components.An example of functional dedication is the use of separate dedicated address and data lines, which is common on many buses, However, it is not essential. For example, addresN8 and data information may b6 transmitted over the same set of lines using an Address Valid contirol line. At the beginning of a data transfer, the
address is placed on the bus and the Address Valid line is activated. At this point,each module has a specified period of time to copy the address and determine if it is the addressed module, The address is then removed from the bus, and the same bus connections are used for the subsequent read or write data transfer. This method of using the same line for multiple purposes is known as time multiplexing.
The advantage of time multiplexing is the use of fewer lines, which saves space and, usually, cost. The disadvantago is that more complex circuitry is needed within each module. Also, there is a potontial reduction in performance because certain events that share the same lines cannot take place in parallel.
Physical dedication refers to the use of multiple buses, each of which connects only
a subset of modules. A typical example is the use of an I/O bus to interconnect all I/O
modules; this bus is then connected to the main bus through some type of I/O adapter
module, The potential advantage of physical dedication is high throughput, because
there is less bus contention. A disandvantage is the increased size and cost of the system.
Method of Arbitration In all but the simplest systems, more than one module may
need control of the bus. For example, an I/O module may need to read or write directly
to memory, without sending the data to the processor. Because only one unit at a time
can successfully transmit over the bus, some method of arbitration is needed. The vari-
ous methods can be roughly classified as being either centralized or distributed. In a
centralized scheme, a single hardware device, referred to as a bus controller or arbiter, is
responsible for allocating time on the bus, The device may be a separate module or part
of the processor. In a distributed scheme, there is no central controller. Rather, each
module contains access control logic and the modules act together to share the bus. With
both methods of arbitration, the purpose is to designate one device, either the processor
or an I/O module, as master. The master may then initiate a data transfer (e.g, read or
write) with some other device, which acts as slave for this particular exchange.
Timing timing refers to the way in which events are coordinated on the bus. Buses
use either synchronous timing or asynchronous timing.
With synchronous timing, the occurrence of events on the bus is determined by a clock. The bus includes a clock line upon which a clock transmits a regular sequence of alternating 1s and Os of equal duration. A single 1-0 transmission is referred to as a clock cycle or bus cycle and defines a time slot. All other devices on the bus can read the clock line, and all events start at the beginning of a clock cycle.Figure 3.19 shows a typical, but simplified, timing diagram for synchronous read and write operations (see Appendix 3A for a description of timing diagrams). Other bus signals may change at the leading edge of the clock signal (with a slight reaction
delay). Most events occupy a single clock cycle. In this simple example, the processor places a memory address on the address lines during the first clock cycle and may assert various status lines. Once the address lines have stabilized, the processor issues an address enable signal. For a read operation, the processor issues a read command at the start of the second cycle. A memory module recognizes the address
Figure 4 Timing of Synchronous Bus Operations
and, after a delay of one cycle, places the data on the data lines. The processor reads
the data from the data lines and drops the read signal. For a write operation, the
processor puts the data on the data lines at the start of the second cycle, and issues a
write command after the data lines have stabilized. The memory module copies the
information from the data lines during the third clock cycle.
With asynchronous timing, the occurrence of one event on a bus follows and depends on the occurrence of a previous event. In the simple read example of Figure 3.20a, the processor places address and status signals on the bus. After pausing for these signals to stabilize, it issues a read command, indicating the presence of valid address and control signals. The appropriate memory decodes the address and responds by placing the data on the data line. Once the data lines have stabilized,
the memory module asserts the acknowledged line to signal the processor that the
Figure 5 : timing of Asynchronous Bus Operations
data are available. Once the master has read the data from the data lines, it deasserts
the read signal. This causes the memory module to drop the data and acknowledge
lines. Finally, once the acknowledge line is dropped, the master removes the address
information.
Figure 5b: shows a simple asynchronous write operation. In this case, the master places the data on the data line at the same time that is puts signals on the status and address lines. The memory module responds to the write command by copying the data from the data lines and then asserting the acknowledge line. The master then drops the write signal and the memory module drops the acknowledge signal.
Synchronous timing is simpler to implement and test. However, it is less flexible than asynchronous timing. Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance. With asynchronous timing, a mixture of slow and fast devices, using older and newer technology, can share a bus.
Bus Width We have already addressed the concept of bus width. The width of the
data bus has an impact on system performance: The wider the data bus, the greater the number of bits transferred at one time. The width of the address bus has an
impact on system capacity: The wider the address bus, the greater the range of loca-
tions that can be referenced.
Data Transfer Type Finally, a bus supports various data transfer types, as illustrated
in Figure 6. All buses support both write (master to slave) and read (slave to master)
transfers. In the case of a multiplexed address/data bus, the bus is first used for specifying the address and then for transferring the data. For a read operation, there is typically a wait while the data is being fetched from the slave to be put on the bus. For
either a read or a write, there may also be a delay if it is necessary to go through Arbitration to gain control of the bus for the remainder of the operation (i.e., seizes the bus
to request a read or write, then seize the bus again to perform a read or write).
In the case of dedicated address and data buses, the address is put on the address bus and remains there while the data are put on the data bus. For a write operation, the master puts the data onto the data bus as soon as the address has stabilized and the slave has had the opportunity to recognize its address. For a read operation, the slave puts the data onto the data bus as soon as it has recognized its
address and has fetched the data.
There are also several combination operations that some buses allow.A read-modify-write operation is simply a read followed immediately by a write to the same address. The address is only broadcast once at the beginning of the operation. The whole operation is typically indivisible to prevent any access to the data element by other potential bus masters. The principal purpose of this
capability is to protect shared memory resources in a multiprogramming system.
Read-after-write is an indivisible operation consisting of a write followed immediately by a read from the same address. The read operation may be performed for checking purposes.
Some bus systems also support a block data transfer. In this case, one address cycle is followed by n data cycles. The first data item is transferred to or from the specified address
the remaining data items are transferred to or from subsequent addresses.
Figure 6: bus data transfer type
PCI
The peripheral component interconnect (PCI) is a popular high-bandwidth, processor-
independent bus that can function as a mezzanine or peripheral bus. Compared with
other common bus specifications, PCI delivers better system performance for high-speed I/O subsystems (e.g., graphic display adapters, network interface controllers, disk controllers, and so on). The current standard allows the use of up to 64 data lines at 66 MHz, for a raw transfer rate of 528 MByte/s, or 4.224 Gbps. But it is not just a highspeed that makes PCI attractive. PCI is specifically designed to meet economically the I/O requirements of modern systems; it requires very few chips to implement and supports other buses attached to the PCI bus.
Intel began work on PCI in 1990 for its Pentium-based systems. Intel soon
released all the patents to the public domain and promoted the creation of an industry
association, the PCI SIG, to develop further and maintain the compatibility of the PCI
specifications. The result is that PCI has been widely adopted and is finding increasing
use in personal computer, workstation, and server systems. Because the specification
is in the public domain and is supported by a broad cross section of the microproces-
sor and peripheral industry, PCI products built by different vendors are compatible.
PCI is designed to support a variety of microprocessor-based configurations,
including both single- and multiple-processor systems. Accordingly, it provides a general-purpose set of functions. It makes use of synchronous timing and a centralized arbitration scheme.
Figure 7a shows a typical use of PCI in a single-processor system. A combined DRAM controller and bridge to the PCI bus provides tight coupling with the processor and the ability to deliver data at high speeds. The bridge acts as a data buffer so that the speed of the PCI bus may differ from that of the processor's I/O capability. In a multiprocessor system (Figure 7b), one or more PCI configurations may be connected by bridges to the processor's system bus. The system bus
supports only the processor/cache units, main memory, and the PCI bridges. Again,the use of bridges keeps the PCI independent of the processor speed yet provides the ability to receive and deliver data rapidly.
Bus Structure
PCI may be configured as a 32- or 64-bit bus. Table 3.3 defines the 49 mandatory
signal lines for PCI. These are divided into the following functional groups:
• System pins: Include the clock and reset pins.
• Address and data pins: Include 32 lines that are time multiplexed for addresses
and data. The other lines in this group are used to interpret and validate the
signal lines that carry the addresses and data.
• Interface control pins: Control the timing of transactions and provide coordi-
nation among initiators and targets.
• Arbitration pins: Unlike the other PCI signal lines, these are not shared lines.
Rather, cach PCI master has its own pair of arbitration lines that connect it
directly to the PCI bus arbiter.
• Error reporting pins: Used to report parity and other errors.
In addition, the PCI specification defines 51 optional signal lines (Table 1),
divided into the following functional groups:
• Interrupt pins: These are provided for PCI devices that must generate requests
for service. As with the arbitration pins, these are not shared lines. Rather, each
PCI device has its own interrupt line or lines to an interrupt controller.
• Cache support pins: These pins are needed to support a memory on PCI that
can be cached in the processor or another device. These pins support snoopy
cache protocols (see Chapter 18 for a discussion of such protocols).
• 64-bit bus extension pins: Include 32 lines that are time multiplexed for addresses
and data and that are combined with the mandatory address/data lines to form
Figure 7 Example PCI Configurations
a 64-bit address/data bus. Other lines in this group are used to interpret and vali-
date the signal lines that carry the addresses and data. Finally, there are two lines
that enable two PCI devices to agree to the use of the 64-bit capability.
• JTAG/boundary scan pins: These signal lines support testing procedures defined
in IEEE Standard 1149.1.
A bus is a communication pathway connecting two or more devices, A key characteristic of a bus is that it is a shared transmission medium, Multiple devices connect to the bus, and a signal transmitted by any one device is available for reception by all other devices attached to the bus. If two devices transmit during the same time period, their signals will overlap and become garbled. Thus, only one device at a time can successfully transmit.
Typically, a bus consists of multiple communication pathways, or lines. Each line
is capable of transmitting signals representing binary 1 and binary 0. Over time, a sequence of binary digits can be transmitted across a single line. Taken together, several lines of a bus can be used to transmit binary digits simultaneously (in parallel).For example, an 8-bit unit of data can be transmitted over eight bus lines.
Computer systems contain a number of different buses that provide pathways
between components at various levels of the computer system hierarchy. A bus that
connects major computer components (processor, memory, I/O) is called a system
bus. The most common computer interconnection structures are based on the use of one or more system buses.
Bus Structure
A system bus consists, typically, of from about 50 to hundreds of separate lines. Each line
is assigned a particular meaning or function. Although there are many different bus designs, on any bus the lines can be classified into three functional groups (Figure 3.16):
Figure 3.16 Bus Interconnection Scheme
data, address, and control lines. In addition, there may be power distribution lines that
supply power to the attached modules.
The data lines provide a path for moving data between system modules. These lines, collectively, are called the data bus. The data bus may consist of from 32 to
hundreds of separate lines, the number of lines being referred to as the width of the
data bus. Because each line can carry only 1 bit at a time, the number of lines determines how many bits can be transferred at a time. The width of the data bus is a key factor in determining overall system performance. For example, if the data bus is 8 bits wide and each instruction is 16 bits long, then the processor must access the memory module twice during each instruction cycle.
The address lines are used to designate the source or destination of the data on the data bus. For example, if the processor wishes to read a word (8, 16, or 32 bits) of data from memory, it puts the address of the desired Word on the address lines. Clearly, the width of the address bus determines the maximum possible memory capacity of the system. Furthermore, the address lines are generally also used to address I/O pOrts. Typically, the higher-order bits are used to select a particular module on the bus. and the lower-order bits select a memory location or l/O port within the module. For example, on an 8-bit address bus, address O1IIILII and below might reference locations in a memory module (module 0) With L28 WOrdS ot memory, and address 10000000 and above refer to devices attached to an 1/O module (module 1).
The control lines are used to control the access to and the use of the data and address lines. Because the data and address lines are shared by all Components, there must be a means of controlling their use. Control singals transmit both command and timing information between syntax modules. Timing signals indicate the validity of data and address information. Command signals specify operations to be performed. Typical control lines include
• Memory write: Causes data on the bus to be written into the addressed location
- Memory read: Causes data from the addressed location to be placed on the bus
• I/O read: Causes data from the addressed I/O port to be placed on the bus
• Transfer ACK: Indicates that data have been accepted from or placed on the bus
• Bus request: Indicates that a module needs to gain control of the bus
• Bus grant: Indicates that a requesting module has been granted control of the bus
Interrupt request: Indicates that an interrupt is pending
• Interrupt ACK: Acknowledges that the pending interrupt has been recognized
• Clock: Used to synchronize operations
• Reset: Initializes all modules
The operation of the bus is as follows. If one module wishes to send data to another, it must do two things: (1) Obtain the use of the bus, and (2) transfer data via the bus. If one module wishes to request data from another module, it must (1) obtain the use of the bus, and (2) transfer a request to the other module over the appropriate control and address lines. It must then wait for that second module to send the data. Physically, the system bus is actually a number of parallel electrical conductors. In the classic bus arrangement, these conductors are metal lines etched in a
Figure 2 Typical Physical Realization of a Bus Architecture
card or board (printed circuit board). The bus extends across all of the system components, each of which taps into some or all of the bus lines. The classic physical arrangement is depicted in Figure 2. In this example, the bus consists of two vertical columns of conductors. At regular intervals along the columns, there are attachment points in the form of slots that extend out horizontally to support a printed circuit board. Each of the major system components occupies one or more boards and plugs into the bus at these slots. The entire arrangement is housed in a chassis, This scheme can still be used for some of the buses associated with a computer system. However, modern systems tend to have all of the major components on the same board with more elements on the same chip as the processor. Thus, an on-chip bus may connect the processor and cache memory, whereas an on-board bus may connect the processor to main memory and other components.
This arrangement is most convenient. A small computer system may be acquired and then expanded later (more memory, more I/O) by adding more boards. If a component on a board fails, that board can easily be removed and replaced.
Multiple-Bus Hierarchies
If a great number of devices are connected to the bus, performance will suffer. There
are two main causes:
1. In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay. This delay determines the time it takes for devices to coordinate the use of the bus. When control of the bus passes from one device to another frequently, these propagation delays can
noticeably affect performance.
2. The bus may become a bottleneck as the aggregate data transfer demand approaches the capacity of the bus. This problem can be countered to some extent by increasing the data rate that the bus can carry and by using wider buses (e.g., inereasing the data bus from 32 to 64 bits). However, because the data rates generated by attached devices (e.g., graphics and video controllers,network interfaces) are growing rapidly, this is a race that a single bus is ultimately destined to lose.
Accordingly, most computer systems use multiple buses, generally laid out in a hierarchy. A typical traditional structure is shown in Figure 3a. There is a local bus
that connects the processor to a cache memory and that may support one or more local devices The cache memory controller connects the cache not only to this local bus, but to a system bus to which are attached all of the main memory modules. the use of a cache structure insulates the processor from a requirement to access main memory frequently. Hence, main memory can be
moved off of the local bus onto a system bus. In this way, I/O transfers to and from the main memory across the system bus do not interfere with the processor's activity. It is possible to connect I/O controllers directly onto the system bus. A more efficient solution is to make use of one or more expansion buses for this purpose. An expansion bus interface buffers data transfers between the system bus and the I/O
controllers on the expansion bus. This arrangement allows the system to support a
wide variety of I'O devices and at the same time insulate memory-to-processor traf-
fic from IO traffic.
Figure 3a shows some typical examples of I/O devices that might be attached to the expansion bus Network connections include local area networks(LANS) such as a 10-Mbps Ethernet and connections to wide area networks(WANS) such as a packet-switching network, SCSI (small computer system inter-
face) is itself a type of bus used to support local disk drives and other peripherals.
A serial port could be used to support a printer or scanner.This traditional bus architecture is reasonably efficient but begins to break
down as higher and higher performance is seen in the I/O devices. In response to
these growing demands, a common approach taken by industry is to build a high-speed bus that is closely integrated with the rest of the system, requiring only a bridge between the processor's bus and the high-speed bus. This arrangement is sometimes known as a mezzanine architecture.
Figure 3b shows a typical realization of this approach. Again, there is a local bus that connects the processor to a cache controller, which is in turn connected to a system
bus that supports main memory. The cache controller is integrated into a bridge, or
buffering device, that connects to the high-speed bus. This bus supports connections
to high-speed LANS such as Fast Ethernet at 100 Mbps, video and graphics workstation
controllers, as well as interface controllers to local peripheral buses, including SCSI and
Fire Wire. The latter is a high-speed bus arrangement specifically designed to support
high-capacity I/O devices Lower-speed devices are still supported off an expansion bus,
with an interface buffering traffic between the expansion bus and the high-speed bus.
The advantage of this arrangement is that the high-speed bus brings high-demand devices into closer integration with the processor and at the same time is independent of the processor. Thus, differences in processor and high-speed bus
Figure 3 Example Bus Configurations
speeds and signal line definitions are tolerated. Changes in processor architecture do not affect the high-speed bus, and vice versa.
Elements of Bus Design
Although a variety of different bus implementations exist, there are a few basic parameters or design elements that serve to classify and differentiate buses. Table 1
lists key elements.
Bus Types bus lines on be separated into two generic types: dedicated and Multiplexed. A dedicated bus line is permanently assigned either to one function or to a physical subset of computer components.An example of functional dedication is the use of separate dedicated address and data lines, which is common on many buses, However, it is not essential. For example, addresN8 and data information may b6 transmitted over the same set of lines using an Address Valid contirol line. At the beginning of a data transfer, the
address is placed on the bus and the Address Valid line is activated. At this point,each module has a specified period of time to copy the address and determine if it is the addressed module, The address is then removed from the bus, and the same bus connections are used for the subsequent read or write data transfer. This method of using the same line for multiple purposes is known as time multiplexing.
The advantage of time multiplexing is the use of fewer lines, which saves space and, usually, cost. The disadvantago is that more complex circuitry is needed within each module. Also, there is a potontial reduction in performance because certain events that share the same lines cannot take place in parallel.
Physical dedication refers to the use of multiple buses, each of which connects only
a subset of modules. A typical example is the use of an I/O bus to interconnect all I/O
modules; this bus is then connected to the main bus through some type of I/O adapter
module, The potential advantage of physical dedication is high throughput, because
there is less bus contention. A disandvantage is the increased size and cost of the system.
Method of Arbitration In all but the simplest systems, more than one module may
need control of the bus. For example, an I/O module may need to read or write directly
to memory, without sending the data to the processor. Because only one unit at a time
can successfully transmit over the bus, some method of arbitration is needed. The vari-
ous methods can be roughly classified as being either centralized or distributed. In a
centralized scheme, a single hardware device, referred to as a bus controller or arbiter, is
responsible for allocating time on the bus, The device may be a separate module or part
of the processor. In a distributed scheme, there is no central controller. Rather, each
module contains access control logic and the modules act together to share the bus. With
both methods of arbitration, the purpose is to designate one device, either the processor
or an I/O module, as master. The master may then initiate a data transfer (e.g, read or
write) with some other device, which acts as slave for this particular exchange.
Timing timing refers to the way in which events are coordinated on the bus. Buses
use either synchronous timing or asynchronous timing.
With synchronous timing, the occurrence of events on the bus is determined by a clock. The bus includes a clock line upon which a clock transmits a regular sequence of alternating 1s and Os of equal duration. A single 1-0 transmission is referred to as a clock cycle or bus cycle and defines a time slot. All other devices on the bus can read the clock line, and all events start at the beginning of a clock cycle.Figure 3.19 shows a typical, but simplified, timing diagram for synchronous read and write operations (see Appendix 3A for a description of timing diagrams). Other bus signals may change at the leading edge of the clock signal (with a slight reaction
delay). Most events occupy a single clock cycle. In this simple example, the processor places a memory address on the address lines during the first clock cycle and may assert various status lines. Once the address lines have stabilized, the processor issues an address enable signal. For a read operation, the processor issues a read command at the start of the second cycle. A memory module recognizes the address
Figure 4 Timing of Synchronous Bus Operations
and, after a delay of one cycle, places the data on the data lines. The processor reads
the data from the data lines and drops the read signal. For a write operation, the
processor puts the data on the data lines at the start of the second cycle, and issues a
write command after the data lines have stabilized. The memory module copies the
information from the data lines during the third clock cycle.
With asynchronous timing, the occurrence of one event on a bus follows and depends on the occurrence of a previous event. In the simple read example of Figure 3.20a, the processor places address and status signals on the bus. After pausing for these signals to stabilize, it issues a read command, indicating the presence of valid address and control signals. The appropriate memory decodes the address and responds by placing the data on the data line. Once the data lines have stabilized,
the memory module asserts the acknowledged line to signal the processor that the
Figure 5 : timing of Asynchronous Bus Operations
data are available. Once the master has read the data from the data lines, it deasserts
the read signal. This causes the memory module to drop the data and acknowledge
lines. Finally, once the acknowledge line is dropped, the master removes the address
information.
Figure 5b: shows a simple asynchronous write operation. In this case, the master places the data on the data line at the same time that is puts signals on the status and address lines. The memory module responds to the write command by copying the data from the data lines and then asserting the acknowledge line. The master then drops the write signal and the memory module drops the acknowledge signal.
Synchronous timing is simpler to implement and test. However, it is less flexible than asynchronous timing. Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance. With asynchronous timing, a mixture of slow and fast devices, using older and newer technology, can share a bus.
Bus Width We have already addressed the concept of bus width. The width of the
data bus has an impact on system performance: The wider the data bus, the greater the number of bits transferred at one time. The width of the address bus has an
impact on system capacity: The wider the address bus, the greater the range of loca-
tions that can be referenced.
Data Transfer Type Finally, a bus supports various data transfer types, as illustrated
in Figure 6. All buses support both write (master to slave) and read (slave to master)
transfers. In the case of a multiplexed address/data bus, the bus is first used for specifying the address and then for transferring the data. For a read operation, there is typically a wait while the data is being fetched from the slave to be put on the bus. For
either a read or a write, there may also be a delay if it is necessary to go through Arbitration to gain control of the bus for the remainder of the operation (i.e., seizes the bus
to request a read or write, then seize the bus again to perform a read or write).
In the case of dedicated address and data buses, the address is put on the address bus and remains there while the data are put on the data bus. For a write operation, the master puts the data onto the data bus as soon as the address has stabilized and the slave has had the opportunity to recognize its address. For a read operation, the slave puts the data onto the data bus as soon as it has recognized its
address and has fetched the data.
There are also several combination operations that some buses allow.A read-modify-write operation is simply a read followed immediately by a write to the same address. The address is only broadcast once at the beginning of the operation. The whole operation is typically indivisible to prevent any access to the data element by other potential bus masters. The principal purpose of this
capability is to protect shared memory resources in a multiprogramming system.
Read-after-write is an indivisible operation consisting of a write followed immediately by a read from the same address. The read operation may be performed for checking purposes.
Some bus systems also support a block data transfer. In this case, one address cycle is followed by n data cycles. The first data item is transferred to or from the specified address
the remaining data items are transferred to or from subsequent addresses.
PCI
The peripheral component interconnect (PCI) is a popular high-bandwidth, processor-
independent bus that can function as a mezzanine or peripheral bus. Compared with
other common bus specifications, PCI delivers better system performance for high-speed I/O subsystems (e.g., graphic display adapters, network interface controllers, disk controllers, and so on). The current standard allows the use of up to 64 data lines at 66 MHz, for a raw transfer rate of 528 MByte/s, or 4.224 Gbps. But it is not just a highspeed that makes PCI attractive. PCI is specifically designed to meet economically the I/O requirements of modern systems; it requires very few chips to implement and supports other buses attached to the PCI bus.
Intel began work on PCI in 1990 for its Pentium-based systems. Intel soon
released all the patents to the public domain and promoted the creation of an industry
association, the PCI SIG, to develop further and maintain the compatibility of the PCI
specifications. The result is that PCI has been widely adopted and is finding increasing
use in personal computer, workstation, and server systems. Because the specification
is in the public domain and is supported by a broad cross section of the microproces-
sor and peripheral industry, PCI products built by different vendors are compatible.
PCI is designed to support a variety of microprocessor-based configurations,
including both single- and multiple-processor systems. Accordingly, it provides a general-purpose set of functions. It makes use of synchronous timing and a centralized arbitration scheme.
Figure 7a shows a typical use of PCI in a single-processor system. A combined DRAM controller and bridge to the PCI bus provides tight coupling with the processor and the ability to deliver data at high speeds. The bridge acts as a data buffer so that the speed of the PCI bus may differ from that of the processor's I/O capability. In a multiprocessor system (Figure 7b), one or more PCI configurations may be connected by bridges to the processor's system bus. The system bus
supports only the processor/cache units, main memory, and the PCI bridges. Again,the use of bridges keeps the PCI independent of the processor speed yet provides the ability to receive and deliver data rapidly.
Bus Structure
PCI may be configured as a 32- or 64-bit bus. Table 3.3 defines the 49 mandatory
signal lines for PCI. These are divided into the following functional groups:
• System pins: Include the clock and reset pins.
• Address and data pins: Include 32 lines that are time multiplexed for addresses
and data. The other lines in this group are used to interpret and validate the
signal lines that carry the addresses and data.
• Interface control pins: Control the timing of transactions and provide coordi-
nation among initiators and targets.
• Arbitration pins: Unlike the other PCI signal lines, these are not shared lines.
Rather, cach PCI master has its own pair of arbitration lines that connect it
directly to the PCI bus arbiter.
• Error reporting pins: Used to report parity and other errors.
In addition, the PCI specification defines 51 optional signal lines (Table 1),
divided into the following functional groups:
• Interrupt pins: These are provided for PCI devices that must generate requests
for service. As with the arbitration pins, these are not shared lines. Rather, each
PCI device has its own interrupt line or lines to an interrupt controller.
• Cache support pins: These pins are needed to support a memory on PCI that
can be cached in the processor or another device. These pins support snoopy
cache protocols (see Chapter 18 for a discussion of such protocols).
• 64-bit bus extension pins: Include 32 lines that are time multiplexed for addresses
and data and that are combined with the mandatory address/data lines to form
Figure 7 Example PCI Configurations
a 64-bit address/data bus. Other lines in this group are used to interpret and vali-
date the signal lines that carry the addresses and data. Finally, there are two lines
that enable two PCI devices to agree to the use of the 64-bit capability.
• JTAG/boundary scan pins: These signal lines support testing procedures defined
in IEEE Standard 1149.1.
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